The operating frequencies and the number of input/output (I/O) signals of integrated circuits are continuously increasing, while the physical dimensions of the I/O signal contacts are continuously decreasing. The cost of implementing test hardware, such as performance boards (also referred to as load boards), increases as the number and density of I/O signal contacts rises. Technology currently available to conduct signaling from the load board to the device under test (DUT) has difficulty supporting the small contact pitch dimensions of modern integrated circuits. Furthermore, the excessive length of test hardware interconnects, particularly those associated with the load board, detract from signal integrity and can limit the frequency at which the integrated circuit can be tested. Accordingly, an improved technique for testing integrated circuit devices with relatively small contact pitches would be advantageous.